mt8173: Enable dynamic clock management

This patch enables dynamic clock management control to reduce power
consumption in various components.

Change-Id: I8f66d9b72c8b1d70169ffe46cc361b16a0dadb77
Signed-off-by: Jimmy Huang <[email protected]>

diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c
index 03ec690ffa7fb3912e8701c1f2a109129fa0ec1f..ec951432294c936423410a29bd86c3cebe3455a6 100644 (file)
--- a/plat/mediatek/mt8173/bl31_plat_setup.c
+++ b/plat/mediatek/mt8173/bl31_plat_setup.c
@@ -96,6 +96,16 @@ static void platform_setup_cpu(void)
        /* set LITTLE cores arm64 boot mode */
        mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw,
                MP0_CPUCFG_64BIT);
+
+       /* enable dcm control */
+       mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl,
+               ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN |
+               EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN |
+               INFRACLK_PSYS_DYNAMIC_CG_EN);
+       mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl,
+               L2C_SRAM_DCM_EN);
+       mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl,
+               MCU_BUS_DCM_EN);
 }
 
 /*******************************************************************************

diff --git a/plat/mediatek/mt8173/include/mcucfg.h b/plat/mediatek/mt8173/include/mcucfg.h
index d2474ac6198a8f9af6557129f5028c3d2ae6f826..7c837ba725d47c768f76bf0c56bb2c80e16e530f 100644 (file)
--- a/plat/mediatek/mt8173/include/mcucfg.h
+++ b/plat/mediatek/mt8173/include/mcucfg.h
@@ -176,4 +176,70 @@ enum {
        MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
 };
 
+/* cci clock control related */
+enum {
+       MCU_BUS_DCM_EN  = 1 << 8
+};
+
+/* l2c sram control related */
+enum {
+       L2C_SRAM_DCM_EN = 1 << 0
+};
+
+/* bus fabric dcm control related */
+enum {
+       PSYS_ADB400_DCM_EN              = 1 << 29,
+       GPU_ADB400_DCM_EN               = 1 << 28,
+
+       EMI1_ADB400_DCM_EN              = 1 << 27,
+       EMI_ADB400_DCM_EN               = 1 << 26,
+       INFRA_ADB400_DCM_EN             = 1 << 25,
+       L2C_ADB400_DCM_EN               = 1 << 24,
+
+       MP0_ADB400_DCM_EN               = 1 << 23,
+       CCI400_CK_ONLY_DCM_EN           = 1 << 22,
+       L2C_IDLE_DCM_EN                 = 1 << 21,
+
+       CA15U_ADB_DYNAMIC_CG_EN         = 1 << 19,
+       CA7L_ADB_DYNAMIC_CG_EN          = 1 << 18,
+       L2C_ADB_DYNAMIC_CG_EN           = 1 << 17,
+
+       EMICLK_EMI1_DYNAMIC_CG_EN       = 1 << 12,
+
+       INFRACLK_PSYS_DYNAMIC_CG_EN     = 1 << 11,
+       EMICLK_GPU_DYNAMIC_CG_EN        = 1 << 10,
+       EMICLK_EMI_DYNAMIC_CG_EN        = 1 << 8,
+
+       CCI400_SLV_RW_DCM_EN            = 1 << 7,
+       CCI400_SLV_DCM_EN               = 1 << 5,
+
+       ACLK_PSYS_DYNAMIC_CG_EN         = 1 << 3,
+       ACLK_GPU_DYNAMIC_CG_EN          = 1 << 2,
+       ACLK_EMI_DYNAMIC_CG_EN          = 1 << 1,
+       ACLK_INFRA_DYNAMIC_CG_EN        = 1 << 0,
+
+       /* adb400 related */
+       ADB400_GRP_DCM_EN = PSYS_ADB400_DCM_EN | GPU_ADB400_DCM_EN |
+                           EMI1_ADB400_DCM_EN | EMI_ADB400_DCM_EN |
+                           INFRA_ADB400_DCM_EN | L2C_ADB400_DCM_EN |
+                           MP0_ADB400_DCM_EN,
+
+       /* cci400 related */
+       CCI400_GRP_DCM_EN = CCI400_CK_ONLY_DCM_EN | CCI400_SLV_RW_DCM_EN |
+                           CCI400_SLV_DCM_EN,
+
+       /* adb clock related */
+       ADBCLK_GRP_DCM_EN = CA15U_ADB_DYNAMIC_CG_EN | CA7L_ADB_DYNAMIC_CG_EN |
+                           L2C_ADB_DYNAMIC_CG_EN,
+
+       /* emi clock related */
+       EMICLK_GRP_DCM_EN = EMICLK_EMI1_DYNAMIC_CG_EN |
+                           EMICLK_GPU_DYNAMIC_CG_EN |
+                           EMICLK_EMI_DYNAMIC_CG_EN,
+
+       /* bus clock related */
+       ACLK_GRP_DCM_EN = ACLK_PSYS_DYNAMIC_CG_EN | ACLK_GPU_DYNAMIC_CG_EN |
+                         ACLK_EMI_DYNAMIC_CG_EN | ACLK_INFRA_DYNAMIC_CG_EN,
+};
+
 #endif  /* __MCUCFG_H__ */